|
|
| Offered by:
Department of Applied Electronics
(IAE) |
| No credit points with: D4611 |
| Recommended semester:
1st semester |
| Scope and form: Class lectures and lab-work. |
| Examination:
Approval of compulsery exercises and written exam.
(13 point scale
) |
| Remarks: Approval of lab-work before the examination |
| Contact person: |
Jørn Bang, IAE, Building 451, Tel. +45 4525 5236 |
|
Aim: The course objective is to make the student capable of:
- analyzing a combinational network
- transforming a logical problem into one or more equations and to reduce the equations
- transforming logic expressions into truthtables and reverse
- implementing truthtables into 2-gatelevel combinational network
- using simple software for implementing logic in PLD's
- understanding different flip-flop types and understanding state transition diagrams |
Contents: Definition of logic true. Logic true in relation to physical/electrical dimensions. Active/asserted.
Definition of OR- and AND-operators.
Examples with mixed assertion levels on in- and output.
The Inverter. Use of mnemonics. Function tables.
Logic equations from function tables. Reduction of logic expressions.
Karnaugh maps. Reductions based on Karnaugh maps. Variables in Karnaugh maps.
Architecture of simple PLD IC's. Programming of PLD's.
Traditional MSI IC's. Suitability of replacing MSI with PLD's. The binary cell. Flip-flop types. Definition of sequential circuits. Timing diagrams. Simple counters. Bus-systems including tri-state circuits. Timing. |
